At present, engineering for manufacturing integrated circuits employs a projection photolithography system. FIG. 1 is a schematic block diagram of the projection photolithography system. As shown, the light emitted from a light source 1 is converged to a mask plate 3 by a convergent lens. The image on the mask passes through a set of lenses 4, 5 and forms a reduced image on a silicon wafer 6, thus, a target pattern is obtained by means of photolithography. Since the projection photolithography system performs projection imaging by isomg a mask for the pattern of a whole chip, a large viewing field is needed, which restricts the resolution of the image. Further, with the existing projection photolithography, the wavelength of an incident light has been reduced to 260 nm, the numerical aperture (NA) of a lens has reached 0.8, and the minimum line-width of a circuit has reached 0.18 μm, all of which have approached to the physical limits. Therefore, the potential for increasing the minimum line-width is limited.
Additionally, with the above projection scheme, for each set of circuits, one set of masks is prepared, thus, it is bound to increase the production cost. Especially for small batch production, the cost of each chip enormously rises.